Sciweavers

22 search results - page 5 / 5
» Trace Cache: A Low Latency Approach to High Bandwidth Instru...
Sort
View
JSA
2000
116views more  JSA 2000»
13 years 7 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
MICRO
2008
IEEE
131views Hardware» more  MICRO 2008»
14 years 1 months ago
Token flow control
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha