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DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 4 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
WOSP
2004
ACM
14 years 3 months ago
Collecting whole-system reference traces of multiprogrammed and multithreaded workloads
The simulated evaluation of memory management policies relies on reference traces—logs of memory operations performed by running processes. No existing approach to reference tra...
Scott F. Kaplan
CGO
2003
IEEE
14 years 3 months ago
Dynamic Trace Selection Using Performance Monitoring Hardware Sampling
Optimizing programs at run-time provides opportunities to apply aggressive optimizations to programs based on information that was not available at compile time. At run time, prog...
Howard Chen, Wei-Chung Hsu, Dong-yuan Chen
IPPS
1999
IEEE
14 years 2 months ago
Visualization and Performance Prediction of Multithreaded Solaris Programs by Tracing Kernel Threads
Efficient performance tuning of parallel programs is often hard. We present a performance prediction and visualization tool called VPPB. Based on a monitored uni-processor executi...
Magnus Broberg, Lars Lundberg, Håkan Grahn
JPDC
2010
106views more  JPDC 2010»
13 years 8 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller