204 search results - page 20 / 41 » Trace Processors |
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
LCPC
2007
Springer
14 years 2 months ago
2007
Springer
Recent studies have shown that programming in a Partition Global Address Space (PGAS) language can be more productive than programming in a message passing model. One reason for th...
IEEEPACT
2007
IEEE
14 years 2 months ago
2007
IEEE
Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology ...
ICCS
2009
Springer
14 years 3 months ago
2009
Springer
Abstract. Contemporary high-end Terascale and Petascale systems are composed of hundreds of thousands of commodity multi-core processors interconnected with high-speed custom netwo...
ISPDC
2008
IEEE
14 years 3 months ago
2008
IEEE
We present a load-balancing technique that exploits the temporal coherence, among successive computation phases, in mesh-like computations to be mapped on a cluster of processors....