Sciweavers

204 search results - page 34 / 41
» Trace Processors
Sort
View
PLDI
1995
ACM
13 years 11 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
CHES
2008
Springer
144views Cryptology» more  CHES 2008»
13 years 9 months ago
Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs
Abstract. This paper proposes new chosen-message power-analysis attacks against public-key cryptosystems based on modular exponentiation, which use specific input pairs to generate...
Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Ak...
ISCAPDCS
2003
13 years 8 months ago
Utilization of Separate Caches to Eliminate Cache Pollution Caused by Memory Management Functions
Data intensive service functions such as memory allocation/de-allocation, data prefetching, and data relocation can pollute processor cache in conventional systems since the same ...
Mehran Rezaei, Krishna M. Kavi
HPDC
2010
IEEE
13 years 8 months ago
LogGOPSim: simulating large-scale applications in the LogGOPS model
We introduce LogGOPSim--a fast simulation framework for parallel algorithms at large-scale. LogGOPSim utilizes a slightly extended version of the well-known LogGPS model in combin...
Torsten Hoefler, Timo Schneider, Andrew Lumsdaine
ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
13 years 7 months ago
TurboTag: lookup filtering to reduce coherence directory power
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...
Pejman Lotfi-Kamran, Michael Ferdman, Daniel Crisa...