204 search results - page 5 / 41 » Trace Processors |
RTCSA
1999
IEEE
14 years 25 days ago
1999
IEEE
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
HPCC
2007
Springer
14 years 2 months ago
2007
Springer
Although event tracing of parallel applications offers highly detailed performance information, tracing on current leading edge systems may lead to unacceptable perturbation of the...
IEEEPACT
1999
IEEE
14 years 25 days ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
ACMMSP
2004
ACM
14 years 2 months ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
AINA
2007
IEEE
14 years 2 months ago
2007
IEEE
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...