Pipeline Timing Analysis Using a Trace-Driven Simulator

In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipeline modeling. Our technique handle CPUs that execute multiple shorter instructions in parallel with long-running instructions. The results of other machine analyses, like cache analysis, can be used in our pipeline analysis. Also, results from high-level program ow analysis can be used to tighten the execution time predictions. Our primary target is embedded real-time systems, and since processor simulators are standard equipment for embedded development work, our tool will be easy to port to relevant target processors.

• Type: Conference
• Year: 1999
• Where: RTCSA
• Authors: Jakob Engblom, Andreas Ermedahl
• Keywords: Embedded Systems, Execution Time, RTCSA 1999, Technique Handle Cpus, Time WCET Analysis