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» Trace-Level Speculative Multithreaded Architecture
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IPPS
2008
IEEE
14 years 1 months ago
Reducing the run-time of MCMC programs by multithreading on SMP architectures
The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov Chain Mont...
Jonathan M. R. Byrd, Stephen A. Jarvis, A. H. Bhal...
HPCA
2005
IEEE
14 years 20 days ago
Chip Multithreading: Opportunities and Challenges
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...
Lawrence Spracklen, Santosh G. Abraham
SPAA
2004
ACM
14 years 14 days ago
The potential in energy efficiency of a speculative chip-multiprocessor
While lower supply voltage is effective for energy reduction, it suffers performance loss. To mitigate the loss, we propose to execute only the part, which does not have any influ...
Yuu Tanaka, Toshinori Sato, Takenori Koushiro
ASPLOS
2008
ACM
13 years 9 months ago
Accurate branch prediction for short threads
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to e...
Bumyong Choi, Leo Porter, Dean M. Tullsen
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 9 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar