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110
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DAC
1997
ACM
15 years 8 months ago
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
Avaneendra Gupta, John P. Hayes
117
Voted
OOPSLA
1992
Springer
15 years 8 months ago
A Comparative Performance Evaluation of Write Barrier Implementations
Generational garbage collectors are able to achieve very small pause times by concentrating on the youngest (most recently allocated) objects when collecting, since objects have b...
Antony L. Hosking, J. Eliot B. Moss, Darko Stefano...
DELTA
2006
IEEE
15 years 8 months ago
Using Design Patterns to Overcome Image Processing Constraints on FPGAs
The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resourc...
K. T. Gribbon, Donald G. Bailey, Christopher T. Jo...
120
Voted
ESA
2006
Springer
130views Algorithms» more  ESA 2006»
15 years 8 months ago
Reporting Flock Patterns
Data representing moving objects is rapidly getting more available, especially in the area of wildlife GPS tracking. It is a central belief that information is hidden in large data...
Marc Benkert, Joachim Gudmundsson, Florian Hü...
ANSS
1991
IEEE
15 years 8 months ago
A provably correct, non-deadlocking parallel event simulation algorithm
This paper first summerizes and then presents a formal proof to a new conservative deadlock-free algorithm, YADDES [l], for asynchronous discrete event simulation. The proof not o...
Meng-Lin Yu, Sumit Ghosh, Erik DeBenedictis