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DAC
2012
ACM
11 years 11 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
ECOOPW
1998
Springer
14 years 27 days ago
Mapping Business Processes to Software Design Artifacts
This paper explains the structure of a project repository, which enables you to trace business processes and business rules to the architecture and design of the software system. T...
Pavel Hruby
IPPS
2008
IEEE
14 years 3 months ago
Financial modeling on the cell broadband engine
High performance computing is critical for financial markets where analysts seek to accelerate complex optimizations such as pricing engines to maintain a competitive edge. In th...
Virat Agarwal, Lurng-Kuo Liu, David A. Bader
WSC
2004
13 years 10 months ago
Implementing the High Level Architecture in the Virtual Test Bed
The Virtual Test Bed (VTB) is a prototype of a virtual engineering environment to study operations of current and future space vehicles, spaceports, and ranges. The HighLevel Arch...
José A. Sepúlveda, Luis C. Rabelo, J...
SIGSOFT
2003
ACM
14 years 1 months ago
Modeling and validation of service-oriented architectures: application vs. style
Most applications developed today rely on a given middleware platform which governs the interaction between components, the access to resources, etc. To decide, which platform is ...
Luciano Baresi, Reiko Heckel, Sebastian Thöne...