Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs

Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more efficient memory hierarchy for multi-core architectures. Although the high density, low leakage and high endurance are attractive features of STTRAM, the latency and energy overhead associated with write operations are major obstacles for being competitive with the SRAM. Our study shows that the non-volatility feature with years of data-retention time for STT-RAM technology is not necessary for its usage in on-chip cache, since the refresh times of cache data are usually in µs (for L1 cache) or ms (for L2 cache) range. Thus, we propose to trade-off the non-volatility (data-retention time) of STT-RAM for better write performance/energy for designing STT-RAM-based L2 cache. The paper addresses several critical design issues such as how we decide on a suitable retention time for last level cache, what the rela...

• Type: Journal
• Year: 2012
• Where: DAC
• Authors: Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das
• Keywords: Computer Architecture, DAC 2012, Memory Hierarchy, Non Volatile Memory, Volatility Data