264 search results - page 48 / 53 » Transaction level modeling: an overview |
CODES
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
CODES
2009
IEEE
14 years 2 days ago
2009
IEEE
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
UAI
2007
13 years 8 months ago
2007
The traditional approach to building Bayesian networks is to build the graphical structure using a graphical editor and then add probabilities using a separate spreadsheet for eac...
ISN
1999
Springer
13 years 11 months ago
1999
Springer
The ACTS FlowThru project aims to build a management system which supports the flow of management information across organisational and technological domains by reusing components ...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...