20 search results - page 1 / 4 » Transforming loops to recursion for multi-level memory hiera... |
PLDI
2000
ACM
13 years 11 months ago
2000
ACM
IJPP
2006
13 years 7 months ago
2006
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
ICPPW
2002
IEEE
14 years 11 days ago
2002
IEEE
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transf...
PCI
2005
Springer
14 years 28 days ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...