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IEEEPACT
2007
IEEE
14 years 1 months ago
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
Brian Greskamp, Josep Torrellas
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
14 years 1 months ago
A hybrid framework for design and analysis of fault-tolerant architectures
It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus t...
Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Va...
IPPS
2006
IEEE
14 years 1 months ago
A self-stabilizing minimal dominating set algorithm with safe convergence
A self-stabilizing distributed system is a faulttolerant distributed system that tolerates any kind and any finite number of transient faults, such as message loss and memory cor...
Hirotsugu Kakugawa, Toshimitsu Masuzawa
PRDC
2005
IEEE
14 years 1 months ago
Partitioned Cache Shadowing for Deep Sub-Micron (DSM) Regime
An important issue in modern cache designs is bridging the gap between wire and device delays. This warrants the use of more regular and modular structures to mask wire latencies....
Heng Xu, Arun K. Somani
DSN
2003
IEEE
14 years 23 days ago
On the Design of Robust Integrators for Fail-Bounded Control Systems
This paper describes the design and evaluation of a robust integrator for software-implemented control systems. The integrator is constructed as a generic component in the Simulin...
Jonny Vinter, Andréas Johansson, Peter Folk...