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» Trusted Design in FPGAs
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JSAC
2006
181views more  JSAC 2006»
13 years 7 months ago
Information theoretic framework of trust modeling and evaluation for ad hoc networks
Abstract-- The performance of ad hoc networks depends on cooperation and trust among distributed nodes. To enhance security in ad hoc networks, it is important to evaluate trustwor...
Yan Lindsay Sun, Wei Yu, Zhu Han, K. J. Ray Liu
ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 7 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 18 days ago
Reducing pin and area overhead in fault-tolerant FPGA-based designs
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...
SAMOS
2005
Springer
14 years 26 days ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 23 days ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar