3 search results - page 1 / 1 » Tuning Blocked Array Layouts to Exploit Memory Hierarchy in ... |
PCI
2005
Springer
14 years 1 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
Strassen’s matrix multiplication (MM) has benefits with respect to any (highly tuned) implementations of MM because Strassen’s reduces the total number of operations. Strasse...
EUROPAR
2000
Springer
13 years 11 months ago
2000
Springer
With the increasing processing power, the latency of the memory hierarchy becomes the stumbling block of many modern computer architectures. In order to speed-up the calculations, ...