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ATS
1998
IEEE
76views Hardware» more  ATS 1998»
13 years 12 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
HPCA
1998
IEEE
13 years 12 months ago
Virtual-Physical Registers
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
Antonio González, José Gonzál...
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
13 years 12 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
HOTSWUP
2009
ACM
13 years 11 months ago
Efficient Systematic Testing for Dynamically Updatable Software
Recent years have seen significant advances in dynamic software updating (DSU) systems, which allow programs to be patched on the fly. However, a significant challenge remains: Ho...
Christopher M. Hayden, Eric A. Hardisty, Michael W...
PASTE
1998
ACM
13 years 11 months ago
Efficient Composite Data Flow Analysis Applied to Concurrent Programs
FLAVERS, a tool for verifying properties of concurrent systems, uses composite data flow analysis to incrementally improve the precision of the results of its verifications. Altho...
Gleb Naumovich, Lori A. Clarke, Leon J. Osterweil