67 search results - page 12 / 14 » Two Techniques for Improvement the Speedup of Nautilus DSM |
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabi...
CASES
2003
ACM
14 years 1 months ago
2003
ACM
Software thread integration (STI) is a compilation technique which enables the efficient use of an application’s fine-grain idle time on generic processors without special hardw...
PPOPP
2003
ACM
14 years 1 months ago
2003
ACM
Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threa...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
TC
2008
13 years 7 months ago
2008
Recent studies have shown that, in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...