524 search results - page 19 / 105 » Two efficient methods to reduce power and testing time |
173
click to vote
TCAD
2008
15 years 4 months ago
2008
Abstract--This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an o...
140
click to vote
CW
2002
IEEE
15 years 9 months ago
2002
IEEE
For sparse array operations, in general, the sparse arrays are compressed by some data compression schemes in order to obtain better performance. The Compressed Row/Column Storage...
119
click to vote
DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
155
click to vote
CIKM
2006
Springer
15 years 8 months ago
2006
Springer
We consider the problem of finding highly correlated pairs in a large data set. That is, given a threshold not too small, we wish to report all the pairs of items (or binary attri...
148
click to vote
HICSS
2005
IEEE
15 years 10 months ago
2005
IEEE
Abstract— We compare two alternative mechanisms for capping prices in two-settlement electricity markets. With sufficient lead time and competitive entry opportunities, forward ...