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» Two efficient methods to reduce power and testing time
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SDM
2008
SIAM
139views Data Mining» more  SDM 2008»
15 years 5 months ago
Proximity Tracking on Time-Evolving Bipartite Graphs
Given an author-conference network that evolves over time, which are the conferences that a given author is most closely related with, and how do they change over time? Large time...
Hanghang Tong, Spiros Papadimitriou, Philip S. Yu,...
TWC
2008
154views more  TWC 2008»
15 years 4 months ago
MEERA: Cross-Layer Methodology for Energy Efficient Resource Allocation in Wireless Networks
Abstract-- In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the sys...
Sofie Pollin, Rahul Mangharam, Bruno Bougard, Lies...
CGF
2005
159views more  CGF 2005»
15 years 4 months ago
Real-Time Shape Editing using Radial Basis Functions
Current surface-based methods for interactive freeform editing of high resolution 3D models are very powerful, but at the same time require a certain minimum tessellation or sampl...
Mario Botsch, Leif Kobbelt
ATS
1998
IEEE
76views Hardware» more  ATS 1998»
15 years 8 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
TCAD
2008
136views more  TCAD 2008»
15 years 4 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar