58 search results - page 5 / 12 » UML Modeling and Formal Verification of Control Data Driven ... |
DAC
2008
ACM
2008
ACM
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
14 years 8 months ago
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In t...
ECMDAFA
2005
Springer
14 years 1 months ago
2005
Springer
This article presents a control flow analysis methodology based on UML 2.0 sequence diagrams (SD). In contrast to the conventional code-based control flow analysis techniques, thi...
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
We present a framework for formal verification of embedded custom memories. Memory verification is complicated ifficulty in abstracting design parameters induced by the inherently ...
ACSD
2001
IEEE
13 years 11 months ago
2001
IEEE
We present a new way to define the semantics of imperative synchronous languages by means of separating the control and the data flow. The control flow is defined by predicates th...
IFIPTCS
2000
13 years 11 months ago
2000
Masaccio is a formal model for hybrid dynamical systems which are built from atomic discrete components (di erence equations) and atomic continuous components (di erential equation...