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CODES
2002
IEEE
14 years 11 days ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
14 years 1 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
FPL
1997
Springer
130views Hardware» more  FPL 1997»
13 years 11 months ago
Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research
: The paper first proposes requirements for an ideal platform for codesign research. A new board developed at Imperial College, the Riley-2, is shown to meet these requirements. It...
Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Lu...
EMSOFT
2006
Springer
13 years 11 months ago
Multi-level software reconfiguration for sensor networks
In-situ reconfiguration of software is indispensable in embedded networked sensing systems. It is required for re-tasking a deployed network, fixing bugs, introducing new features...
Rahul Balani, Chih-Chieh Han, Ram Kumar Rengaswamy...
CODES
2010
IEEE
13 years 4 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...