Hardware/software optimization of error detection implementation for real-time embedded systems

This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when im...

• Type: Journal
• Year: 2010
• Where: CODES
• Authors: Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izosimov
• Keywords: CODES 2010, Error Detection, Error Detection Implementation, Software Engineering, Transient Faults