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DSN
2007
IEEE
14 years 2 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
ETFA
2005
IEEE
14 years 1 months ago
Assessment of PROFIBUS networks using a fault injection framework
Industrial control systems architectures have been evolving to the decentralization of control tasks. This evolution associated with the time-critical nature of these tasks, incre...
J. A. Carvalho, A. S. Carvalho, Paulo Portugal
DATE
2004
IEEE
110views Hardware» more  DATE 2004»
13 years 11 months ago
Interactive Cosimulation with Partial Evaluation
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimizatio...
Patrick Schaumont, Ingrid Verbauwhede
ICDCS
2008
IEEE
14 years 2 months ago
PFC: Transparent Optimization of Existing Prefetching Strategies for Multi-Level Storage Systems
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
Zhe Zhang, Kyuhyung Lee, Xiaosong Ma, Yuanyuan Zho...
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
13 years 11 months ago
On the Design and Verification Methodology of the Look-Aside Interface
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Moha...