24 search results - page 2 / 5 » UPPAAL - a Tool Suite for Automatic Verification of Real-Tim... |
FM
2009
Springer
13 years 6 months ago
2009
Springer
Abstract. We propose an approach to automatic verification of realtime systems against scenario-based requirements. A real-time system is modeled as a network of Timed Automata (TA...
FORMATS
2007
Springer
14 years 13 days ago
2007
Springer
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
CODES
2008
IEEE
13 years 10 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
FTCS
1998
13 years 10 months ago
1998
Ensuring the correctness of computer systems used in lifecritical applications is very difficult. The most commonly used verification methods, simulation and testing, are not exha...