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» Ultra low power digital signal processing
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DELTA
2010
IEEE
14 years 28 days ago
Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor
Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of...
Hans G. Kerkhoff, Xiao Zhang
FPGA
2009
ACM
200views FPGA» more  FPGA 2009»
14 years 2 months ago
FPGA-based front-end electronics for positron emission tomography
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
Michael Haselman, Robert Miyaoka, Thomas K. Lewell...
CORR
2010
Springer
158views Education» more  CORR 2010»
13 years 2 months ago
Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
ISLPED
1999
ACM
86views Hardware» more  ISLPED 1999»
14 years 4 days ago
Power macro-models for DSP blocks with application to high-level synthesis
Abstract – In this paper, we propose a modeling approach for the average power consumption of macro-blocks that are typically used in digital signal processing (DSP) systems, suc...
Subodh Gupta, Farid N. Najm
ICASSP
2009
IEEE
13 years 5 months ago
A game theoretical algorithm for joint power and topology control in distributed WSN
In this paper, the issue of network topology control in wireless networks using a fully distributed algorithm is considered. Whereas the proposed distributed algorithm is designed...
Pau Closas, Alba Pages-Zamora, Juan A. Ferná...