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» Ultra-low power digital subthreshold logic circuits
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ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
14 years 5 months ago
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits
In this work we propose a methodology to self-consistently solve leakage power with temperature to predict thermal runaway. We target 28nm FinFET based circuits as they are more p...
Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz,...
ISCAS
2006
IEEE
135views Hardware» more  ISCAS 2006»
14 years 2 months ago
Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
Volkan Kursun, Zhiyu Liu
CAL
2007
13 years 8 months ago
Logic-Based Distributed Routing for NoCs
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
José Flich, José Duato
DAC
2005
ACM
14 years 9 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
14 years 15 days ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia