Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
- In this paper, we present a prototype FPGA design for an efficient physical layer implementation of a MIMO-OFDM technique. We propose a pipelined architecture using a Fast Fourie...
Jeoong Sung Park, Hong-Jip Jung, Viktor K. Prasann...
: -RetinotopicNET is an efficient simulator for neural networks with retinotopic-like receptive fields. The system has two main characteristics: it is event-driven and it takes adv...
We present a new approach to the supervised learning of lateral interactions for the competitive layer model (CLM) dynamic feature binding architecture. The method is based on con...
We address the task of problem determination in a distributed system using probes, or test transactions, which gather information about system components. Effective probing requir...
Mark Brodie, Irina Rish, Sheng Ma, Natalia Odintso...