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» Uncertainty-aware circuit optimization
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ICCD
1997
IEEE
100views Hardware» more  ICCD 1997»
14 years 3 months ago
Optimal Clock Period Clustering for Sequential Circuits with Retiming
Abstract— In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock perio...
Arvind K. Karandikar, Peichen Pan, C. L. Liu
STOC
1989
ACM
96views Algorithms» more  STOC 1989»
14 years 2 months ago
Optimal Size Integer Division Circuits
Division is a fundamental problem for arithmetic and algebraic computation. This paper describes Boolean circuits of bounded fan-in for integer division  nding reciprocals that...
John H. Reif, Stephen R. Tate
DAGSTUHL
2007
14 years 10 days ago
Uniqueness of Optimal Mod 3 Circuits for Parity
In this paper, we prove that the quadratic polynomials modulo 3 with the largest correlation with parity are unique up to permutation of variables and constant factors. As a conseq...
Frederic Green, Amitabha Roy
CORR
2010
Springer
104views Education» more  CORR 2010»
13 years 11 months ago
Heuristic approach to optimize the number of test cases for simple circuits
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circ...
S. M. Thamarai, K. Kuppusamy, T. Meyyappan
ICCAD
1998
IEEE
94views Hardware» more  ICCAD 1998»
14 years 3 months ago
Noise considerations in circuit optimization
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...