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» Understanding POWER multiprocessors
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ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 4 months ago
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor
In this work we propose a methodology for the accurate analysis of the power consumption of interprocessor communication in a MPSoC, and the construction of high-level power macro...
Mirko Loghi, Luca Benini, Massimo Poncino
IPPS
2002
IEEE
14 years 15 days ago
Dynamic Power Management of Multiprocessor Systems
Power management is critical to power-constrained real-time systems. In this paper, we present a dynamic power management algorithm. Unlike other approaches that focus on the trad...
Jinwoo Suh, Dong-In Kang, Stephen P. Crago
ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
12 years 7 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
CORR
2010
Springer
127views Education» more  CORR 2010»
13 years 5 months ago
Towards a communication-theoretic understanding of system-level power consumption
Traditional communication theory focuses on minimizing transmit power. However, communication links are increasingly operating at shorter ranges where transmit power can be signif...
Pulkit Grover, Kristen Ann Woyach, Anant Sahai
ASAP
2009
IEEE
98views Hardware» more  ASAP 2009»
13 years 5 months ago
A Power-Scalable Switch-Based Multi-processor FFT
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M pr...
Bassam Jamil Mohd, Earl E. Swartzlander Jr.