720 search results - page 12 / 144 » Uniform Memory Hierarchies |
ICPP
2002
IEEE
14 years 1 months ago
2002
IEEE
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
ISCA
2010
IEEE
14 years 1 months ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
PCI
2005
Springer
14 years 2 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Currently run-time reconfigurable hardware offers really attractive features for embedded systems, such as flexibility, reusability, high performance and, in some cases, low-power...
LCPC
2005
Springer
14 years 2 months ago
2005
Springer
The goal of this work is a systematic approach to compiler optimization for simultaneously optimizing across multiple levels of the memory hierarchy. Our approach combines compiler...