720 search results - page 12 / 144 » Uniform Memory Hierarchies |
138
Voted
ICPP
2002
IEEE
15 years 8 months ago
2002
IEEE
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
152
Voted
ISCA
2010
IEEE
15 years 9 months ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
145
Voted
PCI
2005
Springer
15 years 9 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
134
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
Currently run-time reconfigurable hardware offers really attractive features for embedded systems, such as flexibility, reusability, high performance and, in some cases, low-power...
140
click to vote
LCPC
2005
Springer
15 years 9 months ago
2005
Springer
The goal of this work is a systematic approach to compiler optimization for simultaneously optimizing across multiple levels of the memory hierarchy. Our approach combines compiler...