720 search results - page 23 / 144 » Uniform Memory Hierarchies |
227
Voted
WMPI
2004
ACM
16 years 27 days ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
215
Voted
OOPSLA
2005
Springer
16 years 1 months ago
2005
Springer
It is now well established that the device scaling predicted by Moore’s Law is no longer a viable option for increasing the clock frequency of future uniprocessor systems at the...
202
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DATE
2009
IEEE
16 years 2 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
192
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ASPDAC
2006
ACM
16 years 1 months ago
2006
ACM
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated tha...
238
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MICRO
1997
IEEE
15 years 11 months ago
1997
IEEE
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...