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ICPPW
2002
IEEE
15 years 9 months ago
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transf...
Jaume Abella, Antonio González, Josep Llosa...
MASCOTS
1998
15 years 5 months ago
Caches as Filters: A New Approach to Cache Analysis
As the processor-memory performance gap continues to grow, so does the need for effective tools and metrics to guide the design of efficient memory hierarchies to bridge that gap....
Dee A. B. Weikle, Sally A. McKee, William A. Wulf
IPPS
2010
IEEE
15 years 2 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem
IJFCS
2010
92views more  IJFCS 2010»
15 years 1 months ago
Collapsing the Hierarchy of Parallel Computational Models
We investigate the computational power of parallel models with directed reconfigurable buses and with shared memory. Based on feasibility considerations present in the literature,...
Stefan D. Bruda, Yuanqiao Zhang
DAWAK
2006
Springer
15 years 8 months ago
Extending Visual OLAP for Handling Irregular Dimensional Hierarchies
Comprehensive data analysis has become indispensable in a variety of environments. Standard OLAP (On-Line Analytical Processing) systems, designed for satisfying the reporting need...
Svetlana Mansmann, Marc H. Scholl