Sciweavers

720 search results - page 38 / 144
» Uniform Memory Hierarchies
Sort
View
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 8 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
CF
2010
ACM
15 years 7 months ago
Global management of cache hierarchies
Cache memories currently treat all blocks as if they were equally important, but this assumption of equally importance is not always valid. For instance, not all blocks deserve to...
Mohamed Zahran, Sally A. McKee
ALIFE
2005
15 years 4 months ago
Self-Organizing Hierarchies in Sensor and Communication Networks
We consider a hierarchical multicellular sensing and communication network, embedded in an ageless aerospace vehicle, that is expected to detect and react to multiple impacts and d...
Mikhail Prokopenko, Peter Wang, Philip Valencia, D...
IPPS
2007
IEEE
15 years 10 months ago
Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
Chun Chen, Jaewook Shin, Shiva Kintali, Jacqueline...
GLVLSI
2008
IEEE
137views VLSI» more  GLVLSI 2008»
15 years 11 months ago
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
Ann Gordon-Ross, Jeremy Lau, Brad Calder