Sciweavers

720 search results - page 98 / 144
» Uniform Memory Hierarchies
Sort
View
SC
2004
ACM
15 years 10 months ago
Big Wins with Small Application-Aware Caches
Large datasets, on the order of GB and TB, are increasingly common as abundant computational resources allow practitioners to collect, produce and store data at higher rates. As d...
Julio C. López, David R. O'Hallaron, Tianka...
PARA
2004
Springer
15 years 9 months ago
A Family of High-Performance Matrix Multiplication Algorithms
During the last half-decade, a number of research efforts have centered around developing software for generating automatically tuned matrix multiplication kernels. These include ...
John A. Gunnels, Fred G. Gustavson, Greg Henry, Ro...
ICPP
2003
IEEE
15 years 9 months ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...
HPCA
2002
IEEE
15 years 9 months ago
Non-Vital Loads
As the frequency gap between main memory and modern microprocessor grows, the implementation and efficiency of on-chip caches become more important. The growing latency to memory ...
Ryan Rakvic, Bryan Black, Deepak Limaye, John Paul...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
15 years 9 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell