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HPCC
2009
Springer
14 years 7 days ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
CONCUR
2001
Springer
14 years 4 days ago
Extended Temporal Logic Revisited
A key issue in the design of a model-checking tool is the choice of the formal language with which properties are specified. It is now recognized that a good language should exten...
Orna Kupferman, Nir Piterman, Moshe Y. Vardi
EUROPAR
2001
Springer
14 years 3 days ago
Building TMR-Based Reliable Servers Despite Bounded Input Lifetimes
This paper is on the construction of a server subsystem in a client/server system in an application context where the number of potential clients can be arbitrarily large. The imp...
Paul D. Ezhilchelvan, Jean-Michel Hélary, M...
ICS
2001
Tsinghua U.
14 years 2 days ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
HPCA
2000
IEEE
14 years 1 days ago
A Prefetching Technique for Irregular Accesses to Linked Data Structures
Prefetching offers the potential to improve the performance of linked data structure (LDS) traversals. However, previously proposed prefetching methods only work well when there i...
Magnus Karlsson, Fredrik Dahlgren, Per Stenstr&oum...