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OSDI
2008
ACM
16 years 4 months ago
Memory-aware Scheduling for Energy Efficiency on Multicore Processors
Memory bandwidth is a scarce resource in multicore systems. Scheduling has a dramatic impact on the delay introduced by memory contention, but also on the effectiveness of frequen...
Andreas Merkel, Frank Bellosa
ISCAS
2008
IEEE
154views Hardware» more  ISCAS 2008»
15 years 10 months ago
7-decades tunable translinear SiGe BiCMOS 3-phase sinusoidal oscillator
— A fully differential translinear 3-phase sinusoidal oscillator architecture is presented. The architecture is meant for BiCMOS implementation and uses only NPN devices, typical...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
HICSS
2007
IEEE
124views Biometrics» more  HICSS 2007»
15 years 10 months ago
Building a Coordination Framework to Support Behavior-Based Adaptive Checkpointing for Open Distributed Embedded Systems
Checkpointing is a commonly used approach to provide fault-tolerance and improve system dependability. However, using a constant and preconfigured checkpointing frequency may comp...
Nianen Chen, Shangping Ren
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
14 years 7 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
COMCOM
2002
112views more  COMCOM 2002»
15 years 3 months ago
Decoupling different time scales of network QoS systems
Providing quality of service (QoS) in large-scale networks like the Internet inherently needs to deal with heterogeneous network QoS systems. Therefore, the interworking between d...
Jens Schmitt, Oliver Heckmann, Martin Karsten, Ral...