122 search results - page 4 / 25 » User-controllable coherence for high performance shared memo... |
IEEEPACT
1999
IEEE
14 years 1 days ago
1999
IEEE
The performance of applications on large shared-memory multiprocessors with coherent caches depends on the interaction between the granularity of data sharing, the size of the coh...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
VLDB
2001
ACM
14 years 5 days ago
2001
ACM
Recent research addressed the importance of optimizing L2 cache utilization in the design of main memory indexes and proposed the so-called cache-conscious indexes such as the CSB...
ICPP
1994
IEEE
13 years 12 months ago
1994
IEEE
We assert that in order to perform well, a shared-memory multiprocessorinter-process communication (IPC)facility mustavoid a) accessing any shared data, and b) acquiring any locks...
IPPS
2000
IEEE
14 years 4 days ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...