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IEEEPACT
2009
IEEE
14 years 2 months ago
Quantifying the Potential of Program Analysis Peripherals
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...
Mohit Tiwari, Shashidhar Mysore, Timothy Sherwood
POPL
1998
ACM
13 years 12 months ago
Putting Pointer Analysis to Work
This paper addresses the problem of how to apply pointer analysis to a wide variety of compiler applications. We are not presenting a new pointer analysis. Rather, we focus on put...
Rakesh Ghiya, Laurie J. Hendren
DSL
1997
13 years 9 months ago
Experience with a Language for Writing Coherence Protocols
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
Satish Chandra, James R. Larus, Michael Dahlin, Br...
CN
2010
95views more  CN 2010»
13 years 7 months ago
Loop-free alternates and not-via addresses: A proper combination for IP fast reroute?
The IETF currently discusses fast reroute mechanisms for IP networks (IP FRR). IP FRR accelerates the recovery in case of network element failures and avoids micro-loops during re...
Michael Menth, Matthias Hartmann, Rüdiger Mar...
BMCBI
2005
122views more  BMCBI 2005»
13 years 7 months ago
A neural strategy for the inference of SH3 domain-peptide interaction specificity
Background: The SH3 domain family is one of the most representative and widely studied cases of so-called Peptide Recognition Modules (PRM). The polyproline II motif PxxP that gen...
Enrico Ferraro, Allegra Via, Gabriele Ausiello, Ma...