Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
The Verifying Compiler (VC) project is a core component of the Dependable Systems Evolution Grand Challenge. The VC offers the promise of automatically proving that a program or c...
This paper concerns the use of static analysis for debugging purposes of declarative object-oriented equation-based modeling languages. We propose a framework where over- and unde...
Simulation is a mean for verifying the quality of an architectural specification. Some approaches have been proposed in the past. Each approach has its own internal simulation eng...
We reflect on our experiences from work on the design and semantic underpinnings of Extended ML, a specification language which supports the specification and formal development o...