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» Using Constraints for Exploring Catalogs
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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
EDBT
2010
ACM
155views Database» more  EDBT 2010»
14 years 1 months ago
Reducing metadata complexity for faster table summarization
Since the visualization real estate puts stringent constraints on how much data can be presented to the users at once, table summarization is an essential tool in helping users qu...
K. Selçuk Candan, Mario Cataldi, Maria Luis...
CODES
2007
IEEE
14 years 1 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
ICNP
2007
IEEE
14 years 1 months ago
PSM-throttling: Minimizing Energy Consumption for Bulk Data Communications in WLANs
— While the 802.11 power saving mode (PSM) and its enhancements can reduce power consumption by putting the wireless network interface (WNI) into sleep as much as possible, they ...
Enhua Tan, Lei Guo, Songqing Chen, Xiaodong Zhang
ASPDAC
2005
ACM
138views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Crowdedness-balanced multilevel partitioning for uniform resource utilization
In this paper, we propose a new multi-objective multilevel K-way partitioning which is aware of resource utilization distribution, assuming the resource utilization for a partitio...
Yongseok Cheon, Martin D. F. Wong