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IEEEPACT
2003
IEEE
14 years 20 days ago
Constraint Graph Analysis of Multithreaded Programs
This paper presents a framework for analyzing the performance of multithreaded programs using a model called a constraint graph. We review previous constraint graph definitions fo...
Harold W. Cain, Mikko H. Lipasti, Ravi Nair
PLDI
2003
ACM
14 years 19 days ago
Automatically proving the correctness of compiler optimizations
We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. We first present a domainspeci...
Sorin Lerner, Todd D. Millstein, Craig Chambers
SIGSOFT
2003
ACM
14 years 8 months ago
ARCHER: using symbolic, path-sensitive analysis to detect memory access errors
Memory corruption errors lead to non-deterministic, elusive crashes. This paper describes ARCHER (ARray CHeckER) a static, effective memory access checker. ARCHER uses path-sensit...
Yichen Xie, Andy Chou, Dawson R. Engler
DSD
2008
IEEE
95views Hardware» more  DSD 2008»
14 years 1 months ago
Programmable Numerical Function Generators for Two-Variable Functions
This paper proposes a design method and programmable architectures for numerical function generators (NFGs) of two-variable functions. To realize a two-variable function in hardwa...
Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 7 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...