Variable Input Delay CMOS Logic for Low Power Design

Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized "permanently on" series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design ...

• Type: Conference
• Year: 2005
• Where: VLSID
• Authors: Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
• Keywords: Computer Architecture, Input Delay Cmos, Output Delay Irrespective, Variable Input Delay, VLSID 2005