Sciweavers

49 search results - page 3 / 10
» Using FORAY Models to Enable MPSoC Memory Optimizations
Sort
View
ICDE
2012
IEEE
252views Database» more  ICDE 2012»
11 years 11 months ago
Fuzzy Joins Using MapReduce
—Fuzzy/similarity joins have been widely studied in the research community and extensively used in real-world applications. This paper proposes and evaluates several algorithms f...
Foto N. Afrati, Anish Das Sarma, David Menestrina,...
PLDI
2009
ACM
14 years 3 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
IWCC
1999
IEEE
14 years 25 days ago
Optimizing User-Level Communication Patterns on the Fujitsu AP3000
In this paper, we present techniques and algorithms to improve the performance of various communication patterns on message-passing platforms where, for reasons of safety, user-le...
Jeremy E. Dawson, Peter E. Strazdins
EMSOFT
2007
Springer
14 years 2 months ago
Buffer optimization and dispatching scheme for embedded systems with behavioral transparency
Software components are modular and can enable post-deployment update, but their high overhead in runtime and memory is prohibitive for many embedded systems. This paper proposes ...
Jiwon Hahn, Pai H. Chou
ICCAD
2007
IEEE
92views Hardware» more  ICCAD 2007»
14 years 5 months ago
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...