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» Using Genetic Programming and High Level Synthesis to Design...
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116
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VSTTE
2005
Springer
15 years 8 months ago
Verifying Design with Proof Scores
: Verifying design instead of code can be an effective and practical approach to obtaining verified software. This paper argues that proof scores are an attractive method for ver...
Kokichi Futatsugi, Joseph A. Goguen, Kazuhiro Ogat...
148
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CGO
2011
IEEE
14 years 6 months ago
Language and compiler support for auto-tuning variable-accuracy algorithms
—Approximating ideal program outputs is a common technique for solving computationally difficult problems, for adhering to processing or timing constraints, and for performance ...
Jason Ansel, Yee Lok Wong, Cy P. Chan, Marek Olsze...
DAC
2008
ACM
15 years 4 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
133
Voted
IEEEPACT
2005
IEEE
15 years 8 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove
121
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COMPUTER
2002
103views more  COMPUTER 2002»
15 years 2 months ago
SimpleScalar: An Infrastructure for Computer System Modeling
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...
Todd M. Austin, Eric Larson, Dan Ernst