643 search results - page 108 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
SIGGRAPH
1999
ACM
14 years 1 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
LCN
2006
IEEE
14 years 2 months ago
2006
IEEE
Network server consolidation has become popular through recent virtualization technology that builds secure, isolated network systems on shared hardware. One of the virtualization...
CRV
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents the groundwork for a distributed network of collaborating, intelligent surveillance cameras, implemented with low-cost embedded microprocessor camera modules. ...
MICRO
2003
IEEE
14 years 2 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
ISPDC
2010
IEEE
13 years 7 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...