643 search results - page 116 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
EUROMICRO
2005
IEEE
14 years 2 months ago
2005
IEEE
Code revision of a leading telecom product was performed, combining manual audit and static analysis tools. On average, one exploitable vulnerability was found for every 4000 line...
MSS
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper presents the RAM Enhanced Disk Cache Project, REDCAP, a new cache of disk blocks which reduces the read I/O time by using a small portion of the main memory. The essent...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
PLDI
2011
ACM
12 years 11 months ago
2011
ACM
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...