Sciweavers

643 search results - page 122 / 129
» Using Hardware Counters to Automatically Improve Memory Perf...
Sort
View
CF
2005
ACM
13 years 11 months ago
Evaluation of extended dictionary-based static code compression schemes
This paper evaluates how much extended dictionary-based code compression techniques can reduce the static code size. In their simplest form, such methods statically identify ident...
Martin Thuresson, Per Stenström
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
14 years 2 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
HPCA
2011
IEEE
13 years 10 days ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
ML
2000
ACM
244views Machine Learning» more  ML 2000»
13 years 8 months ago
Learnable Evolution Model: Evolutionary Processes Guided by Machine Learning
A new class of evolutionary computation processes is presented, called Learnable Evolution Model or LEM. In contrast to Darwinian-type evolution that relies on mutation, recombinat...
Ryszard S. Michalski
IEEEPACT
2005
IEEE
14 years 2 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove