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MICRO
2010
IEEE
170views Hardware» more  MICRO 2010»
13 years 6 months ago
Tolerating Concurrency Bugs Using Transactions as Lifeguards
Abstract--Parallel programming is hard, because it is impractical to test all possible thread interleavings. One promising approach to improve a multi-threaded program's relia...
Jie Yu, Satish Narayanasamy
CANPC
1999
Springer
14 years 29 days ago
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
David Brooks, Margaret Martonosi
CF
2009
ACM
14 years 3 months ago
Strategies for dynamic memory allocation in hybrid architectures
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
Peter Bertels, Wim Heirman, Dirk Stroobandt
ASPLOS
1998
ACM
14 years 28 days ago
Compiler-Controlled Memory
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
Keith D. Cooper, Timothy J. Harvey
TPCTC
2010
Springer
147views Hardware» more  TPCTC 2010»
13 years 3 months ago
Assessing and Optimizing Microarchitectural Performance of Event Processing Systems
Abstract. Event Processing (EP) systems are being progressively used in business critical applications in domains such as algorithmic trading, supply chain management, production m...
Marcelo R. N. Mendes, Pedro Bizarro, Paulo Marques