Compiler-Controlled Memory

Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level of success. The primary limit on the compiler’s ability to improve memory behavior is its imperfect knowledge about the run-time behavior of the program. The compiler cannot completely predict runtime access patterns. There is an exception to this rule. During the register allocation phase, the compiler often must insert substantial amounts of spill code; that is, instructions that move values from registers to memory and back again. Because the compiler itself inserts these memory instructions, it has more knowledge about them than other memory operations in the program. Spill-code operations are disjoint from the memory manipulations required by the semantics of the program being compiled, and, indeed, the two can interfere in the cache. This paper proposes a hardware solution to the problem of increased...

• Type: Conference
• Year: 1998
• Where: ASPLOS
• Authors: Keith D. Cooper, Timothy J. Harvey
• Keywords: ASPLOS 1998, Main Memory, Main Memory Hierarchy, Memory Operations, Programming Languages