643 search results - page 89 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
VLDB
1999
ACM
14 years 1 months ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
DSN
2007
IEEE
14 years 22 days ago
2007
IEEE
This paper presents the design and implementation of a real-time behavior profiling system for high-speed Internet links. The profiling system uses flow-level information from con...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Linked data structure (LDS) accesses are critical to the performance of many large scale applications. Techniques have been proposed to prefetch such accesses. Unfortunately, many...
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...